Programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs), may be configured to provide user-defined features. In this regard, PLDs typically include large numbers of logic blocks and/or other components interconnected through various signal paths.
During operation, data signals passed through such signal paths may be latched into flip-flops by various clock signals. For data signals to be properly clocked through the PLD, the data signals and clock signals must be properly synchronized. However, excessive delays of the data signals or clock signals can lead to undesirable results. For example, if a clock signal is excessively delayed with respect to a data signal (e.g., the clock signal fails to arrive at a destination flip-flop before the next data signal by at least a hold time period), then a “double clocking” condition can occur. In this case, if the value of the data signal changes before a previous value of the data signal is clocked in to the destination flip-flop (e.g., before a corresponding clock signal arrives at the destination flip-flop), then the previous value of the data signal will be lost.
In another example, if a data signal is excessively delayed with respect to a clock signal (e.g., the current data signal fails to arrive at a destination flip-flop before the clock signal by at least a setup time period), then a “zero clocking” condition can occur. In this case, if the value of the data signal does not change before a previous value of the data signal is stored by the destination flip-flop (e.g., before a corresponding clock signal arrives at the destination flip-flop), then the previous value of the data signal will be incorrectly clocked into the destination flip-flop.
Various approaches have been developed to address such double clocking and zero clocking concerns. In some approaches, data signals may be delayed by, for example, routing the data signals through slow interconnects and/or detours, thereby increasing the lengths of the data paths. However, such approaches can greatly increase the time required to prepare PLD configurations and, in many cases, cannot guarantee improved performance, especially for very congested designs. Moreover, such approaches often utilize an “all or nothing” approach which limits their usefulness in finding at least partial solutions to synchronization problems.
Accordingly, there is a need for an improved approach to the adjustment of signal paths through a PLD to properly synchronize data signals with clock signals through the PLD.